-- Scorpion turbo by KOE library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity sc_koe is port ( CLK_7MHZ, IORQ, WR_EN, RAM, TRB_IN, H0, H1, M1:in std_logic; WE, CLK_CPU, WAITT, H1M, WR_BUF, RAS: out std_logic); end sc_koe; architecture qwer of sc_koe is signal RRAS, WWE, portdelay1, portdelay0, WR_BUFF: std_logic; signal p13, TRB, WWAITT: std_logic; signal startwait, blok, WAITturbo, WAITneturbo: std_logic; begin WR_BUFF <= not(H0 and not(H1)); startwait <= not(WR_EN) and RAM; process (CLK_7MHZ) begin if (CLK_7MHZ'event and CLK_7MHZ = '0') then if (blok = '0' and WWAITT = '0') then blok <= '1'; elsif (WWAITT = '1') then blok <= (RRAS or H1); end if; end if; end process; process (CLK_7MHZ) begin if (CLK_7MHZ'event and CLK_7MHZ = '1') then if (H1 = '1' and startwait = '0') then TRB <= TRB_IN; end if; RRAS <= H0; portdelay0 <= not(portdelay1) or (IORQ or not(M1)); portdelay1 <= portdelay0; WAITturbo <= (startwait or (blok and not(WR_BUFF))); end if; end process; process (RRAS, H1) begin if (H1 = '1') then WWE <= '1'; elsif (RRAS'event and RRAS = '0') then WWE <= not(WR_EN); end if; end process; process (RAM, WR_BUFF) begin if (WR_BUFF = '0') then WAITneturbo <= '1'; elsif (RAM'event and RAM = '0') then WAITneturbo <= M1; end if; end process; WWAITT <= (WAITturbo and portdelay0) when (TRB = '1') else WAITneturbo when (TRB = '0'); WAITT <= WWAITT; H1M <= H1; WR_BUF <= not(WR_BUFF); CLK_CPU <= (CLK_7MHZ and TRB) or (RRAS and not(TRB)); WE <= WWE; RAS <= RRAS; end qwer;