keeper wrote:Это что такое?
Ну тестбенч тебе пишет, что обнаруженный результат не совпадает с ожидаемым. Т.е., например, ожидали в такоето время единицу, а при симуляции там получился ноль.
keeper wrote:# ** Warning: */MCELL HOLD Low VIOLATION ON DATAIN WITH RESPECT TO CLK;# Expected := 1.3 ns; Observed := 0.986 ns; At : 29785659.156 ns# Time: 29785659156 ps Iteration: 0 Instance: /test_zcspi/dut/\spi1|COUNTER_rtl_0|p8c[0]|6\/preg# ** Warning: */MCELL SETUP High VIOLATION ON DATAIN WITH RESPECT TO CLK;# Expected := 2.9 ns; Observed := 0.062 ns; At : 29839800.594 ns# Time: 29839800594 ps Iteration: 0 Instance: /test_zcspi/dut/\spi1|COUNTER_rtl_0|p8c[0]|5\/preg
cnt : std_logic_vector(7 downto 0) := (others => '0'); -- Начальное значение счетчика
x : std_logic := '0'; -- Начальное значение сигнала
lvd wrote:Ты гейтлевел после квартуса что ли моделишь?
lvd wrote:Да и ещё, глядя на 2 картинку, заметил, что cnt в иксах (X).
process(CLC)
begin
if CLC'event and CLC = '1' then
COUNTER_EN <= not COUNTER(3) or COUNTER(2) or COUNTER(1) or COUNTER(0);
end if;
end process;
process(CLC)
begin
if CLC'event and CLC = '0' then
if START = '1' then
COUNTER <= "1111";
elsif COUNTER_EN = '1' then
COUNTER <= COUNTER + "0001";
end if;
end if;
end process;
deathsoft wrote:А вообще - квартус фтопку, промоделируй сначала проект чисто в модельсиме, и тестбенч напиши сам а не в квартусе диаграммой.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity SPI is
port(
--INPUTS
DI : in std_logic_vector(7 downto 0);
CLC : in std_logic;
START : in std_logic;
MISO : in std_logic;
--OUTPUTS
CNT : out std_logic_vector(3 downto 0);
CNT_EN : out std_logic;
DO : out std_logic_vector(7 downto 0);
SCK : out std_logic;
MOSI : out std_logic
);
end;
architecture spi_rtl of SPI is
signal COUNTER : std_logic_vector(3 downto 0);
signal SHIFT_IN : std_logic_vector(7 downto 0);
signal SHIFT_OUT : std_logic_vector(7 downto 0);
signal COUNTER_EN : std_logic;
begin
CNT <= COUNTER;
CNT_EN <= COUNTER_EN;
SCK <= CLC and not COUNTER(3);
DO <= SHIFT_IN;
MOSI <= SHIFT_OUT(7);
process(CLC)
begin
if CLC'event and CLC = '1' then
COUNTER_EN <= not COUNTER(3) or COUNTER(2) or COUNTER(1) or COUNTER(0);
end if;
end process;
process(CLC)
begin
if CLC'event and CLC = '1' then
if COUNTER(3) = '0' then
SHIFT_IN <= SHIFT_IN(6 downto 0)&MISO;
end if;
end if;
end process;
process(CLC)
begin
if CLC'event and CLC = '0' then
if START = '1' then
SHIFT_OUT <= DI;
elsif COUNTER(3) = '0' then
SHIFT_OUT(7 downto 0) <= SHIFT_OUT(6 downto 0)&SHIFT_OUT(0);
end if;
end if;
end process;
process(CLC)
begin
if CLC'event and CLC = '0' then
if START = '1' then
COUNTER <= "1111";
elsif COUNTER_EN = '1' then
COUNTER <= COUNTER + "0001";
end if;
end if;
end process;
end spi_rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ZCSPI is
port(
--BIDIR
D : inout std_logic_vector(7 downto 0) := "ZZZZZZZZ"; --Data Bus
--INPUTS
nRD : in std_logic;
nWR : in std_logic;
nIORQ : in std_logic;
nRES : in std_logic;
CLC : in std_logic;
A : in std_logic_vector(7 downto 0);
MISO : in std_logic;
--OUTPUTS
CNT : out std_logic_vector(3 downto 0);
CNT_EN : out std_logic;
START : out std_logic;
IORQGE : out std_logic;
nRWE : out std_logic;
nSDCS : out std_logic;
SCK : out std_logic;
MOSI : out std_logic
);
end;
architecture rtl of ZCSPI is
signal PORTS_ADDR_A : std_logic;
signal PORTS_ADDR_B : std_logic;
signal PORTS_ADDR : std_logic;
signal PORT_77_CS : std_logic;
signal PORT_57_CS : std_logic;
signal PORT_37_CS : std_logic;
signal PORT_77_WRSTB : std_logic;
signal PORT_77_RDSTB : std_logic;
signal PORT_57_WRSTB : std_logic;
signal PORT_57_RDSTB : std_logic;
signal PORT_37_WRSTB : std_logic;
signal PORT_37_RDSTB : std_logic;
signal PROG_MODE : std_logic;
signal PROG_MODE_RES : std_logic;
signal IO_READ : std_logic;
signal SPI_DO : std_logic_vector(7 downto 0);
signal SPI_DI : std_logic_vector(7 downto 0);
signal SPI_START : std_logic;
COMPONENT SPI
port(
--INPUTS
DI : in std_logic_vector(7 downto 0);
CLC : in std_logic;
MISO : in std_logic;
START : in std_logic;
--OUTPUTS
CNT : out std_logic_vector(3 downto 0);
CNT_EN : out std_logic;
DO : out std_logic_vector(7 downto 0);
SCK : out std_logic;
MOSI : out std_logic
);
END COMPONENT ;
begin
START <= SPI_START;
SPI_START <= PORT_57_RDSTB or PORT_57_WRSTB;
D <= SPI_DO when PORT_57_RDSTB = '1' else "ZZZZZZZZ";
SPI_DI <= D when PORT_57_WRSTB = '1' else "11111111";
spi1: SPI
PORT MAP (START => SPI_START, DI => SPI_DI, CLC => CLC, MISO => MISO,
DO => SPI_DO, SCK => SCK, MOSI => MOSI, CNT => CNT, CNT_EN => CNT_EN);
IO_READ <= not nIORQ and not nRD;
PORTS_ADDR_A <= A(4) and A(2) and A(1) and A(0) and not A(7) and not A(3);
PORTS_ADDR_B <= A(6) or ( not A(6) and A(5));
PORTS_ADDR <= PORTS_ADDR_A and PORTS_ADDR_B;
IORQGE <= PORTS_ADDR or PROG_MODE;
PORT_77_CS <= A(6) and A(5) and PORTS_ADDR and not nIORQ and not PROG_MODE;
PORT_57_CS <= A(6) and not A(5) and PORTS_ADDR and not nIORQ and not PROG_MODE;
PORT_37_CS <= not A(6) and A(5) and PORTS_ADDR and not nIORQ and not PROG_MODE;
PORT_77_WRSTB <= '1' when PORT_77_CS = '1' and nWR = '0' else '0';
PORT_77_RDSTB <= '1' when PORT_77_CS = '1' and nRD = '0' else '0';
PORT_57_WRSTB <= '1' when PORT_57_CS = '1' and nWR = '0' else '0';
PORT_57_RDSTB <= '1' when PORT_57_CS = '1' and nRD = '0' else '0';
PORT_37_WRSTB <= '1' when PORT_37_CS = '1' and nWR = '0' else '0';
PORT_37_RDSTB <= '1' when PORT_37_CS = '1' and nRD = '0' else '0';
PROG_MODE_RES <= IO_READ or not nRES;
nRWE <= nIORQ or nWR or not PROG_MODE;
D(1 downto 0) <= "00" when PORT_77_RDSTB = '1' else "ZZ";
D(7) <= '0' when PORT_37_RDSTB = '1' else 'Z';
process(PORT_37_WRSTB,PROG_MODE_RES)
begin
if PROG_MODE_RES = '1' then
PROG_MODE <= '0';
elsif PORT_37_WRSTB'event and PORT_37_WRSTB = '0' then
PROG_MODE <= D(0);
end if;
end process;
process(PORT_77_WRSTB,nRES)
begin
if nRES = '0' then
nSDCS <= '1';
elsif PORT_77_WRSTB'event and PORT_77_WRSTB = '0' then
nSDCS <= D(1);
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity test_zcspi is
generic (TCPU :time := 285.714 ns);
port(
D : inout std_logic_vector(7 downto 0);
IORQGE : out std_logic; --CPU signal
nRWE : out std_logic;
nSDCS : out std_logic; --SD Card
SCK : out std_logic;
CNT : out std_logic_vector(3 downto 0);
CNT_EN : out std_logic;
START : out std_logic;
MOSI : out std_logic
);
end;
architecture only of test_zcspi is
COMPONENT ZCSPI
port(
--BIDIR
D : inout std_logic_vector(7 downto 0);
--INPUTS
nRD : in std_logic;
nWR : in std_logic;
nIORQ : in std_logic;
nRES : in std_logic;
CLC : in std_logic;
A : in std_logic_vector(7 downto 0);
MISO : in std_logic;
--OUTPUTS
IORQGE : out std_logic;
nRWE : out std_logic;
nSDCS : out std_logic;
SCK : out std_logic;
CNT : out std_logic_vector(3 downto 0);
CNT_EN : out std_logic;
START : out std_logic;
MOSI : out std_logic
);
END COMPONENT ;
signal nRD : std_logic:= '1';
signal nWR : std_logic:= '1';
signal nIORQ : std_logic:= '1';
signal nRES : std_logic:= '1';
signal CLC : std_logic:= '1';
signal A : std_logic_vector(7 downto 0):= "11111111";
signal MISO : std_logic:= '1';
begin
clock : PROCESS
begin
wait for 35.714 ns; CLC <= not CLC;
end PROCESS clock;
sd_data_out : PROCESS
begin
wait for 3795 ns;
MISO <= '1';
wait for 71.428 ns;
MISO <= '0';
wait for 71.428 ns;
MISO <= '0';
wait for 71.428 ns;
MISO <= '1';
wait for 71.428 ns;
MISO <= '0';
wait for 71.428 ns;
MISO <= '1';
wait for 71.428 ns;
MISO <= '1';
wait for 71.428 ns;
MISO <= '0';
wait for 71.428 ns;
end PROCESS sd_data_out;
stimulus : PROCESS
begin
D <= "11111111";
wait for 40 ns; nRES <= '0';
wait for 140 ns; nRES <= '1';
--SPI
wait for 6*TCPU;
--WRITE #57
A <= "01010111";
wait for 10 ns; nIORQ <= '0';wait for 20 ns; nWR <= '0';
D <= "00000000";wait for 2*TCPU;
nWR <= '1';wait for 20 ns; nIORQ <= '1';D <= "ZZZZZZZZ";
--END WRITE #57
A <= "11101110";
wait for 6*TCPU;
--WRITE #57
A <= "01010111";
wait for 10 ns; nIORQ <= '0';wait for 20 ns; nWR <= '0';
D <= "01010101";wait for 2*TCPU;
nWR <= '1';wait for 20 ns; nIORQ <= '1';D <= "ZZZZZZZZ";
--END WRITE #57
A <= "11101110";
wait for 6*TCPU;
--WRITE #57
A <= "01010111";
wait for 10 ns; nIORQ <= '0';wait for 20 ns; nWR <= '0';
D <= "11011011";wait for 2*TCPU;
nWR <= '1';wait for 20 ns; nIORQ <= '1';D <= "ZZZZZZZZ";
--END WRITE #57
A <= "11101110";
wait for 6*TCPU;
--READ #57
A <= "01010111";
nIORQ <= '0';wait for 20 ns; nRD <= '0';
wait for 2*TCPU;
nRD <= '1';wait for 20 ns; nIORQ <= '1';
--END READ #57
A <= "11101110";
wait for 6*TCPU;
--READ #57
A <= "01010111";
nIORQ <= '0';wait for 20 ns; nRD <= '0';
wait for 2*TCPU;
nRD <= '1';wait for 20 ns; nIORQ <= '1';
--END READ #57
A <= "11101110";
wait for 6*TCPU;
--READ #57
A <= "01010111";
nIORQ <= '0';wait for 20 ns; nRD <= '0';
wait for 2*TCPU;
nRD <= '1';wait for 20 ns; nIORQ <= '1';
--END READ #57
A <= "11101110";
wait for 6*TCPU;
--READ #37
A <= "00110111";
nIORQ <= '0';wait for 20 ns; nRD <= '0';
wait for 2*TCPU;
nRD <= '1';wait for 20 ns; nIORQ <= '1';
--END READ #37
A <= "11101110";
wait for 3*TCPU;
--WRITE #37 - PROG MODE ON
A <= "00110111";
wait for 10 ns; nIORQ <= '0';wait for 20 ns; nWR <= '0';
D <= "00000001";wait for 2*TCPU;
nWR <= '1';wait for 20 ns; nIORQ <= '1';D <= "ZZZZZZZZ";
--END WRITE #37
A <= "11101110";
wait for 3*TCPU;
--WRITE #37 - PROG BYTE
A <= "00110111";
wait for 10 ns; nIORQ <= '0';wait for 20 ns; nWR <= '0';
D <= "10000000";wait for 2*TCPU;
nWR <= '1';wait for 20 ns; nIORQ <= '1';D <= "ZZZZZZZZ";
--END WRITE #37
A <= "11101110";
wait for 3*TCPU;
--WRITE #37 - PROG BYTE
A <= "00110111";
wait for 10 ns; nIORQ <= '0';wait for 20 ns; nWR <= '0';
D <= "10001100";wait for 2*TCPU;
nWR <= '1';wait for 20 ns; nIORQ <= '1';D <= "ZZZZZZZZ";
--END WRITE #37
A <= "11101110";
wait for 3*TCPU;
--READ #37 -- PROG MODE OFF
A <= "00110111";
nIORQ <= '0';wait for 20 ns; nRD <= '0';
wait for 2*TCPU;
nRD <= '1';wait for 20 ns; nIORQ <= '1';
--END READ #37
A <= "11101110";
wait for 3*TCPU;
--READ #37
A <= "00110111";
nIORQ <= '0';wait for 20 ns; nRD <= '0';
wait for 2*TCPU;
nRD <= '1';wait for 20 ns; nIORQ <= '1';
--END READ #37
A <= "11101110";
--wait;
end PROCESS stimulus;
dut : ZCSPI
PORT MAP (
D => D,
nRD => nRD,
nWR => nWR,
nIORQ => nIORQ,
nRES => nRES,
CLC => CLC,
A => A,
MISO => MISO,
IORQGE => IORQGE,
nRWE => nRWE,
MOSI => MOSI,
SCK => SCK,
CNT => CNT,
CNT_EN => CNT_EN,
START => START,
nSDCS => nSDCS
);
end only;
keeper wrote:Вот я и не понимаю откуда то взялось Х,
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity SPI is
port(
--INPUTS
DI : in std_logic_vector(7 downto 0);
CLC : in std_logic;
START : in std_logic;
MISO : in std_logic;
WR_EN : in std_logic;
--OUTPUTS
DO : out std_logic_vector(7 downto 0);
SCK : out std_logic;
MOSI : out std_logic
);
end;
architecture spi_rtl of SPI is
signal COUNTER : std_logic_vector(3 downto 0);
signal SHIFT_IN : std_logic_vector(7 downto 0);
signal SHIFT_OUT : std_logic_vector(7 downto 0);
signal COUNTER_EN : std_logic;
signal START_SYNC : std_logic;
begin
SCK <= CLC and not COUNTER(3);
DO <= SHIFT_IN;
MOSI <= SHIFT_OUT(7);
COUNTER_EN <= not COUNTER(3) or COUNTER(2) or COUNTER(1) or COUNTER(0);
process(CLC)
begin
if CLC'event and CLC = '1' then
START_SYNC <= START;
end if;
end process;
process(CLC)
begin
if CLC'event and CLC = '1' then
if COUNTER(3) = '0' then
SHIFT_IN <= SHIFT_IN(6 downto 0)&MISO;
end if;
end if;
end process;
process(CLC)
begin
if CLC'event and CLC = '0' then
if WR_EN = '1' then
SHIFT_OUT <= DI;
else
if COUNTER(3) = '0' then
SHIFT_OUT(7 downto 0) <= SHIFT_OUT(6 downto 0)&'1';
end if;
end if;
end if;
end process;
process(CLC)
begin
if START_SYNC = '1' then
COUNTER <= "1110";
else
if CLC'event and CLC = '0' then
if COUNTER_EN = '1' then
COUNTER(0) <= not COUNTER(0);
COUNTER(1) <= COUNTER(0) xor COUNTER(1);
COUNTER(2) <= (COUNTER(0) and COUNTER(1)) xor COUNTER(2);
COUNTER(3) <= (COUNTER(0) and COUNTER(1) and COUNTER(2)) xor COUNTER(3);
end if;
end if;
end if;
end process;
end spi_rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ZCSPI is
port(
--BIDIR
D : inout std_logic_vector(7 downto 0) := "ZZZZZZZZ"; --Data Bus
--INPUTS
nRD : in std_logic;
nWR : in std_logic;
nIORQ : in std_logic;
nRES : in std_logic;
CLC : in std_logic;
A : in std_logic_vector(7 downto 0);
MISO : in std_logic;
--OUTPUTS
IORQGE : out std_logic;
nRWE : out std_logic;
nSDCS : out std_logic;
SCK : out std_logic;
MOSI : out std_logic
);
end;
architecture rtl of ZCSPI is
signal PORTS_ADDR_A : std_logic;
signal PORTS_ADDR_B : std_logic;
signal PORTS_ADDR : std_logic;
signal PORT_77_CS : std_logic;
signal PORT_57_CS : std_logic;
signal PORT_37_CS : std_logic;
signal PORT_77_WRSTB : std_logic;
signal PORT_77_RDSTB : std_logic;
signal PORT_57_WRSTB : std_logic;
signal PORT_57_RDSTB : std_logic;
signal PORT_37_WRSTB : std_logic;
signal PORT_37_RDSTB : std_logic;
signal PROG_MODE : std_logic;
signal PROG_MODE_RES : std_logic;
signal IO_READ : std_logic;
signal SPI_DO : std_logic_vector(7 downto 0);
signal SPI_DI : std_logic_vector(7 downto 0);
COMPONENT SPI
port(
--INPUTS
DI : in std_logic_vector(7 downto 0);
CLC : in std_logic;
MISO : in std_logic;
START : in std_logic;
WR_EN : in std_logic;
--OUTPUTS
DO : out std_logic_vector(7 downto 0);
SCK : out std_logic;
MOSI : out std_logic
);
END COMPONENT ;
begin
D <= SPI_DO when PORT_57_RDSTB = '1' else "ZZZZZZZZ";
SPI_DI <= D when PORT_57_WRSTB = '1' else "11111111";
spi1: SPI
PORT MAP (START => PORT_57_CS, DI => SPI_DI, CLC => CLC, MISO => MISO,
DO => SPI_DO, SCK => SCK, MOSI => MOSI, WR_EN => PORT_57_WRSTB);
IO_READ <= not nIORQ and not nRD;
PORTS_ADDR_A <= A(4) and A(2) and A(1) and A(0) and not A(7) and not A(3);
PORTS_ADDR_B <= A(6) or ( not A(6) and A(5));
PORTS_ADDR <= PORTS_ADDR_A and PORTS_ADDR_B;
IORQGE <= PORTS_ADDR or PROG_MODE;
PORT_77_CS <= A(6) and A(5) and PORTS_ADDR and not nIORQ and not PROG_MODE;
PORT_57_CS <= A(6) and not A(5) and PORTS_ADDR and not nIORQ and not PROG_MODE;
PORT_37_CS <= not A(6) and A(5) and PORTS_ADDR and not nIORQ and not PROG_MODE;
PORT_77_WRSTB <= '1' when PORT_77_CS = '1' and nWR = '0' else '0';
PORT_77_RDSTB <= '1' when PORT_77_CS = '1' and nRD = '0' else '0';
PORT_57_WRSTB <= '1' when PORT_57_CS = '1' and nWR = '0' else '0';
PORT_57_RDSTB <= '1' when PORT_57_CS = '1' and nRD = '0' else '0';
PORT_37_WRSTB <= '1' when PORT_37_CS = '1' and nWR = '0' else '0';
PORT_37_RDSTB <= '1' when PORT_37_CS = '1' and nRD = '0' else '0';
PROG_MODE_RES <= IO_READ or not nRES;
nRWE <= nIORQ or nWR or not PROG_MODE;
D(1 downto 0) <= "00" when PORT_77_RDSTB = '1' else "ZZ";
D(7) <= '0' when PORT_37_RDSTB = '1' else 'Z';
process(PORT_37_WRSTB,PROG_MODE_RES)
begin
if PROG_MODE_RES = '1' then
PROG_MODE <= '0';
elsif PORT_37_WRSTB'event and PORT_37_WRSTB = '0' then
PROG_MODE <= D(0);
end if;
end process;
process(PORT_77_WRSTB,nRES)
begin
if nRES = '0' then
nSDCS <= '1';
elsif PORT_77_WRSTB'event and PORT_77_WRSTB = '0' then
nSDCS <= D(1);
end if;
end process;
end rtl;
keeper wrote:3032 забита подзавязку
if CLC'event and CLC = '0' then
if COUNTER_EN = '1' then
COUNTER(0) <= not COUNTER(0);
COUNTER(1) <= COUNTER(0) xor COUNTER(1);
COUNTER(2) <= (COUNTER(0) and COUNTER(1)) xor COUNTER(2);
COUNTER(3) <= (COUNTER(0) and COUNTER(1) and COUNTER(2)) xor COUNTER(3);
end if;
end if;
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